xscvsxdsp

VSX Scalar Convert with round Signed Doubleword to Single-Precision format

xscvsxdsp XT,XB

Converts a signed doubleword integer in a VSX register to a single-precision floating-point number and rounds it.

Details

The instruction converts the contents of doubleword element 0 of VSR[XB] from a signed integer to a single-precision floating-point number, rounds it according to the rounding mode specified by FPSCR.RN, and places the result in doubleword element 0 of VSR[XT] in double-precision format. Doubleword element 1 of VSR[XT] is set to zero.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_SI64(VSR[32×BX+B].dword[0])
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN,v)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)
if xx_flag=1 then SetFX(FPSCR.XX)
VSR[32×TX+T].dword[0] ← result64
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
FPSCR.FR ← inc_flag
FPSCR.FI ← xx_flag

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xscvsxdsp vs1, vs3

Encoding

Binary Layout
18
0
T
6
B
11
312
16
BX TX
21
 
Format XX2-form
Opcode 0xF00004E0
Extension VSX
Registers Altered FPSCR

Operands

  • XT
    Target VSX Register
  • XB
    Source VSX Register