xxspltidp

VSX Vector Splat Immediate Double-Precision

xxspltidp XT, IMM

Spatially duplicates a 32-bit immediate (converted to double) into both double elements.

Encoding

Binary Layout

1

0:5

0

6:7

0

8:11

//

12:13

//

14:15

imm0

16:63

 

Format 8RR:D-form

Opcode 0x0500000080040000

Extension VSX

Operands

• XT
  Target
• IMM
  32-bit Value
• IMM32
  Immediate Value

Example

xxspltidp vs1, 1

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction splats the double-precision value formed by concatenating imm0 and imm1 into each doubleword element of VSR[XT].

Operation

if MSR.VSX=0 then VSX_Unavailable()
IMM32 ←imm0<<16 | imm1
VSR[32×TX+T].dword[0] ←bfp64_CONVERT_FROM_BFP(IMM32)
VSR[32×TX+T].dword[1] ←bfp64_CONVERT_FROM_BFP(IMM32)

Programming Note

This instruction is used to replicate a double-precision floating-point value across all elements of a VSX vector register. Ensure that the VSX facility is enabled in the MSR register; otherwise, it will raise an exception. The immediate values imm0 and imm1 are concatenated to form a 32-bit integer, which is then converted to a double-precision float and replicated across the vector. Be cautious of alignment requirements for the target vector register.