xxgenpcvdm

VSX Generate PCV from Doubleword Mask

xxgenpcvdm XT, XB, IMM

Generates a permute control vector (PCV) based on the doubleword mask in VSR[VRB+32] and stores it in VSR[XT].

Details

The instruction generates a permute control vector (PCV) based on the doubleword mask in VSR[VRB+32] and stores it in VSR[XT]. The operation depends on the value of IMM.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
XT ←32×TX+T
if IMM=0b00000 then do  // Big-Endian expansion
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[i].bit[0]=1 then do
      VSR[XT].dword[i].byte[0] ←8×j + 0x00
      VSR[XT].dword[i].byte[1] ←8×j + 0x01
      VSR[XT].dword[i].byte[2] ←8×j + 0x02
      VSR[XT].dword[i].byte[3] ←8×j + 0x03
      VSR[XT].dword[i].byte[4] ←8×j + 0x04
      VSR[XT].dword[i].byte[5] ←8×j + 0x05
      VSR[XT].dword[i].byte[6] ←8×j + 0x06
      VSR[XT].dword[i].byte[7] ←8×j + 0x07
      j ←j + 1
   end
   else do
      VSR[XT].dword[i].byte[0] ←8×i + 0x10
      VSR[XT].dword[i].byte[1] ←8×i + 0x11
      VSR[XT].dword[i].byte[2] ←8×i + 0x12
      VSR[XT].dword[i].byte[3] ←8×i + 0x13
      VSR[XT].dword[i].byte[4] ←8×i + 0x14
      VSR[XT].dword[i].byte[5] ←8×i + 0x15
      VSR[XT].dword[i].byte[6] ←8×i + 0x16
      VSR[XT].dword[i].byte[7] ←8×i + 0x17
   end
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
else if IMM=0b00001 then do  // Big-Endian compression
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[i].bit[0]=1 then do
      VSR[XT].dword[j].byte[0] ←8×i + 0x00
      VSR[XT].dword[j].byte[1] ←8×i + 0x01
      VSR[XT].dword[j].byte[2] ←8×i + 0x02
      VSR[XT].dword[j].byte[3] ←8×i + 0x03
      VSR[XT].dword[j].byte[4] ←8×i + 0x04
      VSR[XT].dword[j].byte[5] ←8×i + 0x05
      VSR[XT].dword[j].byte[6] ←8×i + 0x06
      VSR[XT].dword[j].byte[7] ←8×i + 0x07
   end
   j ←j + 1
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
else if IMM=0b00010 then do  // Little-Endian expansion
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[1-i].bit[0]=1 then do
      VSR[XT].dword[1-i].byte[7] ←8×j + 0x00
      VSR[XT].dword[1-i].byte[6] ←8×j + 0x01
      VSR[XT].dword[1-i].byte[5] ←8×j + 0x02
      VSR[XT].dword[1-i].byte[4] ←8×j + 0x03
      VSR[XT].dword[1-i].byte[3] ←8×j + 0x04
      VSR[XT].dword[1-i].byte[2] ←8×j + 0x05
      VSR[XT].dword[1-i].byte[1] ←8×j + 0x06
      VSR[XT].dword[1-i].byte[0] ←8×j + 0x07
   end
   j ←j + 1
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
else if IMM=0b00011 then do  // Little-Endian compression
   j ←0
do i = 0 to 1
   if VSR[VRB+32].dword[1-i].bit[0]=1 then do
      VSR[XT].dword[1-j].byte[7] ←8×i + 0x00
      VSR[XT].dword[1-j].byte[6] ←8×i + 0x01
      VSR[XT].dword[1-j].byte[5] ←8×i + 0x02
      VSR[XT].dword[1-j].byte[4] ←8×i + 0x03
      VSR[XT].dword[1-j].byte[3] ←8×i + 0x04
      VSR[XT].dword[1-j].byte[2] ←8×i + 0x05
      VSR[XT].dword[1-j].byte[1] ←8×i + 0x06
      VSR[XT].dword[1-j].byte[0] ←8×i + 0x07
   end
   j ←j + 1
end
do i = j to 1
   VSR[XT].dword[i] ←0xUUUU_UUUU_UUUU_UUUU
end
end

Programming Note

This instruction is used to generate a permute control vector (PCV) based on a doubleword mask. Ensure that the VSX facility is enabled in the MSR register before using this instruction. The operation mode (expansion or compression) is determined by the IMM field. Be cautious with alignment and ensure that the input and output vectors are correctly set up to avoid undefined behavior.

Example

xxgenpcvdm vs1, vs3, 1

Encoding

Binary Layout
60
0
XT
6
IMM
11
XB
16
949
 
Format XX2-form
Opcode 0xF00003B5
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • XB
    Source
  • IMM
    Mask
  • VRB
    Source Vector-Specific Register