mfvsrd

Move From VSR Doubleword

mfvsrd RA, XS

Moves the contents of a doubleword element from a Vector-Scalar Register (VSR) to a General Purpose Register (GPR).

Encoding

Binary Layout

31

0:5

S

6:10

RA

11:15

///

16:20

51

21:30

SX

31

 

Format XX1-form

Opcode 0x7C000066

Extension VSX

Operands

• RA
  Target GPR
• XS
  Source VSR

Example

mfvsrd r4, vs1

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of doubleword element 0 of VSR[XS] are placed into GPR[RA]. For SX=0, mfvsrd is treated as a Floating-Point instruction in terms of resource availability. For SX=1, mfvsrd is treated as a Vector instruction in terms of resource availability.

Operation

if SX=0 & MSR.FP=0 then FP_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
GPR[RA] ← VSR[32×SX+S].dword[0]

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
mffprd
mfvrd

Programming Note

For SX=0, mfvsrd is treated as a Floating-Point instruction in terms of resource availability. For SX=1, mfvsrd is treated as a Vector instruction in terms of resource availability.