lxvwsx

Load VSX Vector Word and Splat Indexed

lxvwsx XT, RA, RB

Loads a 32-bit word and replicates it across the vector.

Encoding

Binary Layout

31

0:5

XT

6:10

RA

11:15

RB

16:20

364

21:31

 

Format XX1-form

Opcode 0x7C0002D8

Extension VSX

Operands

• XT
  Target
• RA
  Base
• RB
  Index

Example

lxvwsx vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 32-bit word from memory at address RA + RB, then replicates it across all four 32-bit word positions in the target VSX register XT. This VSX instruction does not affect condition registers or status fields.

Operation

EA ← RA + RB
word ← [EA:EA+3]
for i in 0 to 3:
  XT[32*i:32*i+31] ← word

Programming Note

The lxvwsx instruction is commonly used for loading a word from memory and replicating it across all elements of a VSX vector register. Ensure that the appropriate privilege levels (MSR.VSX or MSR.VEC) are enabled to avoid exceptions. The instruction requires 4-byte alignment for the memory address; unaligned accesses may result in performance penalties or exceptions depending on the system configuration.