xscvdpsxw

VSX Scalar Convert with round to zero Double-Precision to Signed Word

xscvdpsxw XT,XB

Converts a double-precision floating-point number to a signed word, rounding towards zero.

Encoding

Binary Layout

60

0:5

XT

6:10

/

11:15

XB

16:20

352

21:31

 

Format X-form

Opcode 0xF0000160

Extension VSX

Operands

• XT
  Target Vector-Scalar Register
• XB
  Source Vector-Scalar Register

Example

xscvdpsxw vs1, vs3

Registers Altered

FR, FI, VXSNAN, VXCVI

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

This instruction converts the double-precision floating-point number in VSR[XB] to a signed word and places it into word elements 0 and 1 of VSR[XT]. If the operand is positive or +Infinity, 0x7FFF_FFFF is placed. If negative, -Infinity, or NaN, 0x8000_0000 is placed.

Operation

if (VSR[XB][0] is positive or +Infinity) then
    VSR[XT][0:31] <- 0x7FFF_FFFF
else if (VSR[XB][0] is negative, -Infinity, or NaN) then
    VSR[XT][0:31] <- 0x8000_0000
VSR[XT][32:63] <- 0

Programming Note

This instruction is useful for converting double-precision floating-point numbers to a signed word format, with specific handling for edge cases like infinity and NaN. Ensure that the input register contains valid double-precision values to avoid unexpected results. The instruction operates at user privilege level and does not generate exceptions under normal conditions.