xscvdpuxws

VSX Scalar Convert Double-Precision to Unsigned Word format with round to zero

xscvdpuxws XT,XB

Converts a double-precision floating-point value to an unsigned 32-bit integer, rounding towards zero.

Details

The instruction converts the double-precision floating-point value in VSR[XB] to an unsigned 32-bit integer and places the result into word elements 0 and 1 of VSR[XT]. The contents of word elements 2 and 3 of VSR[XT] are set to 0. If the source is a NaN, the result is 0x0000_0000 and VXCVI is set to 1. If the source is an SNaN, VXSNAN is also set to 1.

Pseudocode Operation

if src ≤ Nmin-1 then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if Nmin-1 < src < Nmin then
    T(Nmin)
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src = Nmin then
    T(Nmin)
    fr(0)
    fi(0)
else if Nmin < src < Nmax then
    T(f2i(trunc(src)))
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src = Nmax then
    T(Nmax)
    fr(0)
    fi(0)
else if Nmax < src < Nmax+1 then
    T(Nmax)
    fr(0)
    fi(1)
    fx(XX)
    if error() then invoke system error handler
else if src ≥ Nmax+1 then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if src is a QNaN then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    if error() then invoke system error handler
else if src is a SNaN then
    T(Nmin)
    fr(0)
    fi(0)
    fx(VXCVI)
    fx(VXSNAN)
    if error() then invoke system error handler

Programming Note

['Previous versions of the architecture allowed the contents of word 0 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 of the result register, as is required by this version of the architecture.', 'This instruction can be used to operate on a single-precision source operand.', 'xscvdpuxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode, including xsrdpic which uses the rounding mode specified by RN.']

Example

xscvdpuxws vs1, vs3

Encoding

Binary Layout
60
0
XT
6
/
11
XB
16
288
21
 
Format XX2-form
Opcode 0xF0000120
Extension VSX
Registers Altered FPSCR, VXSNAN, VXCVI, XX

Operands

  • XT
    Target Vector-Scalar Register
  • XB
    Source Vector-Scalar Register