stw

Store Word

stw RS, D(RA)

Stores the low 32 bits of a register to memory.

Encoding

Binary Layout

36

0:5

RS

6:10

RA

11:15

D

16:31

 

Format D-form

Opcode 0x90000000

Extension Base

Operands

• RS
  Source Register
• D
  Displacement
• RA
  Base Register

Example

stw r3, 0(r4)

// Store 32-bit word.

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Store the low 32 bits of RS to the word in memory at the effective address formed by adding the displacement D (sign-extended) to RA, or to the displacement alone if RA is 0. This is a Base category instruction with no status field updates.

Operation

EA ← EXTS(D, 16) + (RA | 0)
MEM(EA, 4) ← RS[32:63]

Programming Note

The stw instruction stores the lower 32 bits of a register into memory. Ensure that the destination address is properly aligned to avoid alignment faults. This instruction operates at user privilege level and will raise an exception if the EA is out of bounds or access permissions are violated.