vsubuhs

Vector Subtract Unsigned Halfword Saturate

vsubuhs vD, vA, vB

Subtracts 8 unsigned halfwords with saturation.

Details

Subtracts each of eight unsigned 16-bit halfwords in vB from the corresponding halfword in vA, with saturation at the unsigned range [0, 65535]. Results below 0 are clamped to 0; no status flags are affected.

Pseudocode Operation

for i in 0 to 7 do
  diff ← vA[i*16:(i+1)*16-1] - vB[i*16:(i+1)*16-1]
  if diff < 0 then
    vD[i*16:(i+1)*16-1] ← 0
  else
    vD[i*16:(i+1)*16-1] ← diff

Programming Note

This instruction is useful for performing element-wise unsigned subtraction on vectors with saturation to handle overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1. Be aware of potential performance implications due to saturation handling, which may affect throughput.

Example

vsubuhs vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1600
21
 
Format VX-form
Opcode 0x10000640
Extension VMX (AltiVec)
Registers Altered MSR, VSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B