vsubuhs

Vector Subtract Unsigned Halfword Saturate

vsubuhs vD, vA, vB

Subtracts 8 unsigned halfwords with saturation.

Details

The Vector Subtract Unsigned Halfword Saturate instruction (vsubuhs) performs an unsigned subtraction of each halfword element from two vector registers. If the result exceeds the maximum value for a halfword, it is saturated to that maximum value.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].hword[i])
   src2 ←EXTZ(VSR[VRB+32].hword[i])
   VSR[VRT+32].hword[i] ←ui16_CLAMP(src1 + ¬src2 + 1)
end
VSCR.SAT ←VSCR.SAT | sat_flag

Programming Note

This instruction is useful for performing element-wise unsigned subtraction on vectors with saturation to handle overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR register is set to 1. Be aware of potential performance implications due to saturation handling, which may affect throughput.

Example

vsubuhs vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1600
21
 
Format VX-form
Opcode 0x10000640
Extension VMX (AltiVec)
Registers Altered MSR, VSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B