bcds.

Decimal Shift VX-form

bcds. VRT,VRA,VRB,PS

Shifts a signed packed decimal value by a specified number of digits and rounds the result.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

23:30

Format VX-form

Opcode 0x100004C1

Extension Decimal Floating-Point

Operands

VRT
Target Vector Register
VRA
Source Vector Register containing the shift count
VRB
Source Vector Register containing the packed decimal value to be shifted
PS
Packed Decimal Sign Control

Example

bcds. v1, v2, v3, 0

Registers Altered

CR6, VSR, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The bcds. instruction shifts a signed packed decimal value in VSR[VRB+32] by a number of digits specified in byte element 7 of VSR[VRA+32]. The result is placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then Vector_Unavailable()
n ← EXTS(VSR[VRA+32].byte[7])
inv_flag ← (VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ← inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
src_sign ← (VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ← (VSR[VRB+32].nibble[0:30] = 0)
lt_flag ← (eq_flag=0) & (src_sign=1)
gt_flag ← (eq_flag=0) & (src_sign=0)
if n > 0 then do     // shift left
    shcnt ← (n<32) ? n : 31
    src.nibble[0:30] ← VSR[VRB+32].nibble[0:30]
    src.nibble[31:61] ← 0
    ox_flag ← (shcnt > 0) & (src.nibble[0:shcnt-1] != 0)
end else do              // shift right
    shcnt ← ((¬n+1)<32) ? (¬n+1) : 31
    src.nibble[0:30] ← 0
    src.nibble[31:61] ← VSR[VRB+32].nibble[0:30]
    result.nibble[0:30] ← src.nibble[31-shcnt:61-shcnt]
    ox_flag ← 0b0
end
result.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
VSR[VRT+32] ← inv_flag ? undefined : result
CR.bit[56] ← inv_flag ? 0b0 : lt_flag
CR.bit[57] ← inv_flag ? 0b0 : gt_flag
CR.bit[58] ← inv_flag ? 0b0 : eq_flag
CR.bit[59] ← inv_flag | ox_flag

Programming Note

The bcds. instruction is used for shifting signed packed decimal values in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The shift amount is determined by byte element 7 of the source register, and the result is stored in the target register. Be cautious with negative shifts as they are treated as right shifts. The instruction updates condition registers for comparison purposes.