xscvqpsqz

VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword

xscvqpsqz VRT,VRB

Converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero.

Encoding

Binary Layout

63

0:5

FRT

6:10

8

11:15

FRB

16:20

836

21:30

Rc

31

 

Format X-form

Opcode 0xFC080688

Extension VSX

Operands

• VRT
  Target Vector-Scalar Register
• VRB
  Source Vector-Scalar Register
• VT
  Target Vector Register

Example

xscvqpsqz v1, v3

Registers Altered

FPSCR (FPRF, FR, FI, VXSNAN, VXCVI)

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a quad-precision floating-point value from the source VSR to a signed 128-bit quadword integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar element is processed. Out-of-range conversions saturate; FPSCR status flags are set appropriately.

Operation

VRT[0:127] ← ConvertToSignedQuadword_RoundTowardZero(VRB[0:127])

Programming Note

The xscvqpsqz instruction converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero. It handles NaNs and infinities by setting VXSNAN or VXCVI flags and raising an exception. Ensure the source register contains a valid quad-precision float; otherwise, handle exceptions appropriately.