xscvqpsqz

VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword

xscvqpsqz VRT,VRB

Converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero.

Details

The xscvqpsqz instruction converts the contents of VSR[VRB+32] (a quad-precision floating-point value) to a signed quadword integer and places the result into doubleword element 0 of VSR[VRT+32]. The conversion rounds towards zero, and special handling is done for NaNs, infinities, and out-of-range values.

Pseudocode Operation

if src is a QNaN then
    fr(0) <- 0
    fi(0) <- 0
    fx(VXCVI) <- 1
    error()
else if src is a SNaN then
    fr(0) <- 0
    fi(0) <- 0
    fx(VXCVI) <- 1
    fx(VXSNAN) <- 1
    error()
elsif src ≤ Nmin-1 then
    fr(0) <- 0
    fi(0) <- 0
    fx(VXCVI) <- 1
    error()
elsif Nmin-1 < src < Nmin then
    if Inexact? then
        T(Nmin)
        fr(0) <- 0
        fi(1) <- 1
        fx(XX) <- 1
        error()
    else
        T(Nmin)
        fr(0) <- 0
        fi(0) <- 0
    endif
else if src = Nmin then
    if Inexact? then
        T(f2i(trunc(src)))
        fr(0) <- 0
        fi(1) <- 1
        fx(XX) <- 1
    else
        T(Nmin)
        fr(0) <- 0
        fi(0) <- 0
    endif
else if Nmin < src < Nmax then
    if Inexact? then
        T(f2i(trunc(src)))
        fr(0) <- 0
        fi(1) <- 1
        fx(XX) <- 1
        error()
    else
        T(f2i(trunc(src)))
        fr(0) <- 0
        fi(0) <- 0
    endif
else if src = Nmax then
    if Inexact? then
        T(Nmax)
        fr(0) <- 0
        fi(1) <- 1
        fx(XX) <- 1
    else
        T(Nmax)
        fr(0) <- 0
        fi(0) <- 0
    endif
else if Nmax < src < Nmax+1 then
    if Inexact? then
        T(Nmax)
        fr(0) <- 0
        fi(1) <- 1
        fx(XX) <- 1
        error()
    else
        T(Nmax)
        fr(0) <- 0
        fi(0) <- 0
    endif
else if src ≥ Nmax+1 then
    fr(0) <- 0
    fi(0) <- 0
    fx(VXCVI) <- 1
    error()
endif

Programming Note

The xscvqpsqz instruction converts a quad-precision floating-point value to a signed quadword integer, rounding towards zero. It handles NaNs and infinities by setting VXSNAN or VXCVI flags and raising an exception. Ensure the source register contains a valid quad-precision float; otherwise, handle exceptions appropriately.

Example

xscvqpsqz v1, v3

Encoding

Binary Layout

FRT

FRB

836

Format X-form

Opcode 0xFC080688

Extension VSX

Registers Altered FPSCR (FPRF, FR, FI, VXSNAN, VXCVI)

Operands

VRT
Target Vector-Scalar Register
VRB
Source Vector-Scalar Register
VT
Target Vector Register