vcmpequh

Vector Compare Equal Halfword

vcmpequh VRT,VRA,VRB
vcmpequh. VRT,VRA,VRB

Compares each halfword of two vector registers and sets the corresponding halfword in the target register to all 1s if they are equal, otherwise all 0s.

Details

For vcmpequh, each halfword of VSR[VRA+32] is compared with the corresponding halfword of VSR[VRB+32]. If they are equal, the corresponding halfword in VSR[VRT+32] is set to all 1s (0xFFFF); otherwise, it is set to all 0s (0x0000).

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()

all_true ←1
all_false ←1
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]
   if src1 = src2 then do
      VSR[VRT+32].hword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].hword[i] ←0x0000
      all_true ←0
   end
end
do i = 0 to 7
   src1 ←VSR[VRA+32].hword[i]
   src2 ←VSR[VRB+32].hword[i]
   if src1 = src2 then do
      VSR[VRT+32].hword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].hword[i] ←0x0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

vcmpequh v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
Rc
21
 
Format VC-form
Opcode 0x10000046
Extension VMX (AltiVec)
Registers Altered CR6

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register