vminsw

Vector Minimum Signed Word

vminsw vD, vA, vB

Compares the signed integer values in each word element of two vector registers and stores the smaller value into a target vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1666

21:31

 

Format VA-form

Opcode 0x10000382

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vminsw vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vminsw, the instruction compares the signed integer values in each word element of VSR[VRA+32] and VSR[VRB+32]. The smaller value is placed into the corresponding word element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    lt_flag ← EXTS(src1) < EXTS(src2)
    VSR[VRT+32].word[i] ← lt_flag=1 ? src1 : src2

Programming Note

This instruction is used to perform element-wise minimum comparison of signed 32-bit integers in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation respects the sign of the integers, so negative numbers are correctly handled as expected in signed comparisons.