stwcix

Store Word Caching Inhibited Indexed X-form

stwcix RS,RA,RB

Stores a word from a source register to memory with caching inhibited.

Details

Stores a 32-bit word from register RS to memory at the address formed by adding RA and RB, with caching inhibited to bypass L1 cache. This instruction is used for I/O operations and memory-mapped device access where cache coherency is not desired. No condition registers or status fields are modified.

Pseudocode Operation

EA ← (RA) + (RB)
[EA] ← (RS)[32:63]

Programming Note

The stwcix instruction is used to store a 32-bit word from a register to memory with caching inhibited, which can be useful for ensuring data consistency between the CPU and external storage. This instruction requires hypervisor privilege (level HV) and should be used sparingly due to its performance impact. Ensure that the destination address is properly aligned to avoid potential exceptions.

Example

stwcix r3, r4, r5

Encoding

Binary Layout
0
0
RS
6
RA
11
RB
16
11100
21
10101
26
 
Format X-form
Opcode 0x7C00072A
Extension Base

Operands

  • RS
    Source General Purpose Register
  • RA
    Base Address General Purpose Register
  • RB
    Index General Purpose Register