stwcix

Store Word Caching Inhibited Indexed X-form

stwcix RS,RA,RB

Stores a word from a source register to memory with caching inhibited.

Details

Stores the contents of the low-order 32 bits of register RS to the memory location addressed by the sum of the contents of register RA (or 0 if RA=0) and register RB. The storage access is performed with caching inhibited, bypassing the data cache. This instruction is a hypervisor-privileged instruction (privilege level HV) introduced in PowerISA v2.05.

Pseudocode Operation

Not available in specification

Programming Note

The stwcix instruction is used to store a 32-bit word from a register to memory with caching inhibited, which can be useful for ensuring data consistency between the CPU and external storage. This instruction requires hypervisor privilege (level HV) and should be used sparingly due to its performance impact. Ensure that the destination address is properly aligned to avoid potential exceptions.

Example

stwcix r3, r4, r5

Encoding

Binary Layout
0
0
RS
6
RA
11
RB
16
11100
21
10101
26
 
Format X-form
Opcode 0x7C00072A
Extension Base

Operands

  • RS
    Source General Purpose Register
  • RA
    Base Address General Purpose Register
  • RB
    Index General Purpose Register