stvebx

Store Vector Element Byte Indexed

stvebx VRS,RA,RB

Stores a byte element from a vector register into memory.

Encoding

Binary Layout

0

0:5

VRS

6:10

RA

11:15

RB

16:31

 

Format X-form

Opcode 0x7C00010E

Extension VMX (AltiVec)

Operands

• VRS
  Vector Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register

Example

stvebx v1, r4, r5

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores the byte element from vector register VRS at the position determined by the effective address RA+RB into memory. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

Operation

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
byte_index ← EA[28:31]
[EA] ← VRS[byte_index]

Programming Note

Unless bits 60:63 of the address are known to match the byte offset of the subject byte element in VSR[VRS+32], software should use Vector Splat to splat the subject byte element before performing the store.