vmrglb
Vector Merge Low Byte
Interleaves low-order bytes.
Details
Merges the eight low-order (rightmost) bytes from vA and vB in an alternating interleaved pattern into vD, with vA bytes in even positions and vB bytes in odd positions. This VMX instruction does not affect any condition or status registers.
Pseudocode Operation
vD[0:7] ← vA[120:127]
vD[8:15] ← vB[120:127]
vD[16:23] ← vA[112:119]
vD[24:31] ← vB[112:119]
vD[32:39] ← vA[104:111]
vD[40:47] ← vB[104:111]
vD[48:55] ← vA[96:103]
vD[56:63] ← vB[96:103]
vD[64:71] ← vA[88:95]
vD[72:79] ← vB[88:95]
vD[80:87] ← vA[80:87]
vD[88:95] ← vB[80:87]
vD[96:103] ← vA[72:79]
vD[104:111] ← vB[72:79]
vD[112:119] ← vA[64:71]
vD[120:127] ← vB[64:71]Programming Note
The vmrglb instruction is useful for merging data from two vectors by alternating bytes into a third vector. Ensure that the target and source registers are properly aligned to avoid unexpected behavior. This instruction requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise an exception. Performance may vary based on the specific implementation and alignment of the data.
Example
Encoding
Operands
-
vD
Target -
vA
Src A -
vB
Src B