vmrgew

Vector Merge Even Word

vmrgew vD, vA, vB

Merges even word elements from two vector registers into a third.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1932

21:31

Format VX-form

Opcode 0x1000078C

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmrgew vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of word element 0 of VSR[VRA+32] are placed into word element 0 of VSR[VRT+32]. The contents of word element 0 of VSR[VRB+32] are placed into word element 1 of VSR[VRT+32]. The contents of word element 2 of VSR[VRA+32] are placed into word element 2 of VSR[VRT+32]. The contents of word element 2 of VSR[VRB+32] are placed into word element 3 of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32].word[0] ←VSR[VRA+32].word[0]
    VSR[VRT+32].word[1] ←VSR[VRB+32].word[0]
    VSR[VRT+32].word[2] ←VSR[VRA+32].word[2]
    VSR[VRT+32].word[3] ←VSR[VRB+32].word[2]

Programming Note

vmrgew is treated as a Vector instruction in terms of resource availability.