vsubsbs

Vector Subtract Signed Byte Saturate

vsubsbs vD, vA, vB

Subtracts 16 signed bytes with saturation.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1792

21:31

Format VX-form

Opcode 0x10000700

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B

Example

vsubsbs vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Subtracts each of 16 signed 8-bit elements in vB from the corresponding element in vA, with saturation to the signed 8-bit range [-128, 127]. If overflow or underflow occurs, the result saturates to the minimum or maximum signed byte value. No condition register fields are affected.

Operation

for i in 0 to 15 do
  result ← vA[8*i:8*i+7] - vB[8*i:8*i+7]
  if result < -128 then vD[8*i:8*i+7] ← -128
  elsif result > 127 then vD[8*i:8*i+7] ← 127
  else vD[8*i:8*i+7] ← result

Programming Note

This instruction is commonly used in applications requiring vectorized arithmetic operations on signed bytes, such as image processing or audio signal processing. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation saturates results to prevent overflow or underflow, which can be crucial for maintaining data integrity in certain applications.