vsubudm

Vector Subtract Unsigned Doubleword Modulo

vsubudm vD, vA, vB

Subtracts the contents of two vector registers and places the result in a third vector register, modulo operation.

Details

Subtracts each of two unsigned 64-bit doublewords in vB from the corresponding doubleword in vA, with results modulo 2^64 (wrapping on underflow). No status flags are affected; this is a VMX/AltiVec arithmetic operation.

Pseudocode Operation

for i in 0 to 1 do
  vD[i*64:(i+1)*64-1] ← (vA[i*64:(i+1)*64-1] - vB[i*64:(i+1)*64-1]) mod 2^64

Programming Note

This instruction is used for performing unsigned doubleword subtraction with modulo arithmetic. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation is performed on each pair of elements from two source vectors, and the results are stored in the destination vector. Be cautious with alignment as it may affect performance or cause exceptions if not properly managed.

Example

vsubudm vd, va, vb

Encoding

Binary Layout
000100
0
vD
6
vA
11
vB
16
10011
21
000000
26
 
Format VX-form
Opcode 0x100004C0
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register