pmxvi8ger4pp

Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate

pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK

Performs a prefixed masked VSX vector 8-bit signed/unsigned integer GER rank-4 update with positive multiply and positive accumulate, adding the result to the accumulator.

Encoding

Binary Layout
59
0:5
AT
6:8
/
9:10
XA
11:15
XB
16:20
2
21:28
AX
29
BX
30
/
31
 
Format MMIRR:XX3-form
Opcode 0x07900000EC000010
Extension MMA

Operands

  • AT
    Target accumulator. ACC[AT] holds a 4x4 matrix of 32-bit signed integer values.
  • XA
    Source VSR supplying four words, each holding four signed 8-bit values.
  • XB
    Source VSR supplying four words, each holding four unsigned 8-bit values.
  • XMSK
    4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero.
  • YMSK
    4-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero.
  • PMSK
    4-bit product mask selecting which of the four byte lanes contribute to each product.

Example

pmxvi8ger4pp

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a prefixed masked VSX vector 8-bit signed/unsigned integer generalized matrix multiply (GER) rank-4 update with positive multiply and positive accumulate semantics, adding the outer product result to the target accumulator register. This instruction is part of the MMA (Matrix-Multiply Assist) extension and uses masking to selectively update the accumulator based on mask fields AT, AX, and BX.

Operation

do i = 0 to 3
  do j = 0 to 3
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then
      psum ← 0
      do k = 0 to 3
        if PMSK.bit[k]=1 then
          psum ← psum + EXTS(VSR[XA].word[i].byte[k]) × EXTZ(VSR[XB].word[j].byte[k])
      ACC[AT][i].word[j] ← CHOP32( psum + EXTS(ACC[AT][i].word[j]) )
    else
      ACC[AT][i].word[j] ← 0

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.