rfebb

Return From Event-Based Branch

rfebb S

Returns control to the address specified by EBBRR0:61 || 0b00 or 320 || EBBRR32:61 || 0b00, depending on MSRSF.

Encoding

Binary Layout

0

0

6

6

11

11

16

16

20

20

21

21

31

31

 

Format XL-form

Opcode 0x4C000124

Extension Base

Operands

• S
  State

Example

rfebb 0

Registers Altered

BESCR, MSR, NIA, EBBRR

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction sets BESCRGE to S and updates NIA based on the event-based branch facility's state. If there are no pending exceptions, it fetches the next instruction from a specific address; otherwise, it generates an event-based branch.

Operation

if 'rfebb' then
    BESCRGE <- S
    if MSRSF=1 then
        NIA <- iea EBBRR0:61 || 0b00
    else
        NIA <- 320 || EBBRR32:61 || 0b00

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction

Programming Note

rfebb serves as both a basic and an extended mnemonic. The Assembler will recognize an rfebb mnemonic with one operand as the basic form, and an rfebb mnemonic with no operand as the intended form. In the extended form, the S operand is omitted and assumed to be 1.