pmxvf16ger2pp

Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate

pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK

Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.

Encoding

Binary Layout

000001

0:5

11100

6:10

1

11

Rc

12

..///

13

///..

14

?

15:63

 

Format MMIRR:XX3-form

Opcode 0x07900000EC000090

Extension MMA

Operands

• AT
  Target accumulator. ACC[AT] holds a 4x4 matrix of 32-bit floating-point values.
• XA
  Source VSR supplying four words, each holding two 16-bit values.
• XB
  Source VSR supplying four words, each holding two 16-bit values.
• XMSK
  4-bit row mask. Row i is updated only when bit i is 1; a masked-off element is set to zero.
• YMSK
  4-bit column mask. Column j is updated only when bit j is 1; a masked-off element is set to zero.
• PMSK
  2-bit product mask selecting which of the two 16-bit lanes contribute to each product.

Example

pmxvf16ger2pp

Related

More in MMA

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

A prefixed masked VSX vector 16-bit floating-point outer-product update (GER rank-2 update) with positive multiply and positive accumulate. This 64-bit MMA instruction requires both prefix and suffix encoding and supports register-based masking for selective accumulator updates.

Operation

do i = 0 to 3
  do j = 0 to 3
    if XMSK.bit[i]=1 & YMSK.bit[j]=1 then
      a0 ← (PMSK.bit[0]=1) ? VSR[XA].word[i].hword[0] : 0
      a1 ← (PMSK.bit[1]=1) ? VSR[XA].word[i].hword[1] : 0
      b0 ← (PMSK.bit[0]=1) ? VSR[XB].word[j].hword[0] : 0
      b1 ← (PMSK.bit[1]=1) ? VSR[XB].word[j].hword[1] : 0
      ACC[AT][i].word[j] ← round(a0 × b0 + a1 × b1) + ACC[AT][i].word[j]
    else
      ACC[AT][i].word[j] ← 0

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.