pmxvf16ger2pp

Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate

pmxvf16ger2pp

Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.

Details

A prefixed masked VSX vector 16-bit floating-point outer-product update (GER rank-2 update) with positive multiply and positive accumulate. This 64-bit MMA instruction requires both prefix and suffix encoding and supports register-based masking for selective accumulator updates.

Pseudocode Operation

for i ∈ [0,7]:
  for j ∈ [0,1]:
    if mask[i,j]:
      ACC[i,j] ← ACC[i,j] + (XA[i] × XB[j])

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

pmxvf16ger2pp

Encoding

Binary Layout
000001
0
11100
6
1
11
Rc
12
..///
13
///..
14
?
15
 
Format MMIRR:XX3-form
Opcode 0x3F800000
Extension MMA

Operands

  • AT
    Target 512-bit accumulator register to be updated based on mask with product accumulation.
  • XA
    VSX vector source register providing the first operand (eight 16-bit FP values).
  • XB
    VSX vector source register providing the second operand (two 16-bit FP values).
  • XM
    VSX vector mask register controlling which accumulator elements are updated.