pmxvf16ger2pp

Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate

pmxvf16ger2pp

Performs a prefixed masked VSX vector 16-bit floating-point GER rank-2 update with positive multiply and positive accumulate.

Details

The pmxvf16ger2pp instruction performs a rank-2 General External Register (GER) update using 16-bit floating-point VSX vector elements, applying masks to select which elements participate in the computation. The operation uses positive multiply and positive accumulate semantics, meaning results are added positively to the accumulator. This is a prefixed instruction using the MMIRR:XX3-form encoding and is part of the MMA (Matrix Multiply Assist) extension introduced in PowerISA v3.1.

Pseudocode Operation

Not available in specification

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

pmxvf16ger2pp

Encoding

Binary Layout
000001
0
11100
6
1
11
Rc
12
..///
13
///..
14
?
15
 
Format MMIRR:XX3-form
Opcode 0x3F800000
Extension MMA

Operands