vpkudum

Vector Pack Unsigned Doubleword Modulo

vpkudum VRT,VRA,VRB

Packs the upper halves of doublewords from two source vectors into a destination vector.

Details

Packs unsigned doubleword elements from source vectors VRA and VRB into a destination vector VRT by selecting the upper halves of each doubleword and concatenating them in pack order. This VMX/AltiVec instruction performs modulo packing without saturation and operates on 64-bit elements.

Pseudocode Operation

VRT[0:63] ← VRA[0:63]
VRT[64:127] ← VRB[0:63]

Programming Note

This instruction is used for packing the upper halves of doublewords from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes each element independently, so there are no ordering requirements between elements, but alignment of input vectors to doubleword boundaries is recommended for optimal performance.

Example

vpkudum v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
1102
21
 
Format VX-form
Opcode 0x1000044E
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register