vpkudum

Vector Pack Unsigned Doubleword Modulo

vpkudum VRT,VRA,VRB

Packs the upper halves of doublewords from two source vectors into a destination vector.

Details

The vpkudum instruction packs the upper halves of doublewords from VSR[VRA+32] and VSR[VRB+32] into VSR[VRT+32]. The contents of bits 32:63 of each doubleword element are placed into word elements of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC then
    Vector_Unavailable()
for i from 0 to 3 do
    VSR[VRT+32].word[i] ← VSR[VRA+32].dword[i].bit[32:63]

Programming Note

This instruction is used for packing the upper halves of doublewords from two source vectors into a destination vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set; otherwise, a Vector Unavailable exception will be raised. The operation processes each element independently, so there are no ordering requirements between elements, but alignment of input vectors to doubleword boundaries is recommended for optimal performance.

Example

vpkudum v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
1102
21
 
Format VX-form
Opcode 0x1000044E
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register