vmuleuh

Vector Multiply Even Unsigned Halfword

vmuleuh vD, vA, vB

Multiplies the even-numbered halfwords of two vector registers and places the results into a destination vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

584

21:31

Format VX-form

Opcode 0x10000248

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vmuleuh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vmuleuh, each pair of even-numbered halfwords from VSR[VRA+32] and VSR[VRB+32] are multiplied, and the 32-bit products are placed into corresponding word elements of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← EXTZ(VSR[VRA+32].hword[2×i])
    src2 ← EXTZ(VSR[VRB+32].hword[2×i])
    VSR[VRT+32].word[i] ← CHOP32(src1 × src2)
end

Programming Note

This instruction multiplies even-numbered halfwords from two vector registers and stores the 32-bit products in another register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. Be cautious of overflow, as only the lower 32 bits of each product are stored. This operation requires the use of VSX (Vector Scalar Extensions) registers.