vand

Vector Logical AND VX-form

vand vD, vA, vB

Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

Details

Performs a bitwise logical AND of the 128-bit contents of vector registers vA and vB, storing the 128-bit result in vector register vD. This operation is performed element-independently across all bits without regard to element boundaries. No status flags are affected.

Pseudocode Operation

vD ← vA & vB

Programming Note

The vand instruction requires the vector facility to be enabled (MSR.VEC=1); otherwise, it will raise a Vector_Unavailable exception. Ensure that the vector registers are properly aligned and initialized before performing operations.

Example

vand vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1028
 
Format VX-form
Opcode 0x10000404
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register