vand

Vector Logical AND VX-form

vand vD, vA, vB

Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

Details

The vand instruction performs a bitwise AND operation on the contents of VSR[VRA+32] and VSR[VRB+32], and places the result into VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
else
    VSR[VRT+32] ← VSR[VRA+32] & VSR[VRB+32]

Programming Note

The vand instruction requires the vector facility to be enabled (MSR.VEC=1); otherwise, it will raise a Vector_Unavailable exception. Ensure that the vector registers are properly aligned and initialized before performing operations.

Example

vand vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1028
 
Format VX-form
Opcode 0x10000404
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register