vand

Vector Logical AND VX-form

vand vD, vA, vB

Performs a bitwise AND operation on the contents of two vector registers and stores the result in another vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1028

21:31

 

Format VX-form

Opcode 0x10000404

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vand vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bitwise logical AND of the 128-bit contents of vector registers vA and vB, storing the 128-bit result in vector register vD. This operation is performed element-independently across all bits without regard to element boundaries. No status flags are affected.

Operation

vD ← vA & vB

Programming Note

The vand instruction requires the vector facility to be enabled (MSR.VEC=1); otherwise, it will raise a Vector_Unavailable exception. Ensure that the vector registers are properly aligned and initialized before performing operations.