vspltisb

Vector Splat Immediate Signed Byte

vspltisb vD, SIM

Splat an immediate signed byte value into all elements of a vector register.

Details

The vspltisb instruction splats the sign-extended 8-bit immediate SIM into all elements of the target vector register VRT.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    VSR[VRT+32].byte[i] ←EXTS8(SIM, 8)
end

Programming Note

This instruction is used to fill a vector register with the sign-extended value of an 8-bit immediate. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The immediate value is sign-extended and replicated across all elements of the target vector register.

Example

vspltisb vd, 4

Encoding

Binary Layout
4
0
vD
6
SIM
11
00000
16
780
 
Format VX-form
Opcode 0x1000030C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • SIM
    Immediate
  • VRT
    Target Vector Register