vspltisb

Vector Splat Immediate Signed Byte

vspltisb vD, SIM

Splat an immediate signed byte value into all elements of a vector register.

Details

Splats a 5-bit signed immediate value into all 16 byte elements of vD, sign-extended to 8 bits per byte. The immediate SIM is a signed 5-bit value (range −16 to 15). No status flags are affected. This is a VMX/AltiVec instruction.

Pseudocode Operation

value ← sign_extend(SIM, 8)
vD ← replicate(value to all 16 byte positions)

Programming Note

This instruction is used to fill a vector register with the sign-extended value of an 8-bit immediate. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The immediate value is sign-extended and replicated across all elements of the target vector register.

Example

vspltisb vd, 4

Encoding

Binary Layout
4
0
vD
6
SIM
11
00000
16
780
 
Format VX-form
Opcode 0x1000030C
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • SIM
    Immediate
  • VRT
    Target Vector Register