slbmte

SLB Move To Entry

slbmte RS, RB

Writes an SLB entry (Mapping effective to virtual address).

Encoding

Binary Layout

31

0:5

RS

6:10

/

11:15

RB

16:20

402

21:30

/

31

 

Format X-form

Opcode 0x7C000324

Extension Privileged

Operands

• RS
  Source VSID
• RB
  Effective Addr

Example

slbmte r3, r5

Registers Altered

MSR

Related

More in Privileged

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Writes an entry to the Segment Lookaside Buffer, mapping an effective segment address (from RB) to a virtual segment ID and protection bits (from RS). This is a privileged 64-bit instruction that modifies virtual address translation state.

Operation

SLB[RB[36:63]] ← RS

Programming Note

The slbmte instruction is used to install temporary ESID-to-VSID translations in the SLB for a specific hardware thread. These entries are thread-specific and can be made permanent (bolted) if LPCRUPRT=1, allowing up to four bolted entries per thread. Ensure that the MSR[PR] bit is clear when executing this instruction, as it requires supervisor privilege level. Be cautious of alignment requirements for the SLB entry data.