srd

Shift Right Doubleword

srd RA, RS, RB

Logical right shift of 64-bit value.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

539

21:31

Format X-form

Opcode 0x7C000436

Extension Base

Operands

RA
Target
RS
Source
RB
Shift Reg

Example

srd r4, r3, r5

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Logically shifts RS right by the number of bit positions specified in RB (bits 57-63), inserting zeros at the left. If RB ≥ 64, the result is zero. No status registers are affected.

Operation

n ← RB[57:63]
if n < 64 then RA ← RS >> n
else RA ← 0

Programming Note

The srd instruction is used to update the Machine State Register (MSR) based on the contents of a source register and the L field. When L=0, specific bits in the MSR are updated using logical operations involving bits from the source register and the current MSR state. When L=1, only bits 48 and 62 of the MSR are set to match those in the source register, while other bits remain unchanged. This instruction requires supervisor privilege level and can trigger exceptions if not executed properly.

srd