lvewx

Load Vector Element Word Indexed

lvewx VRT,RA,RB

Loads a word from memory into a vector register element.

Details

The lvewx instruction loads a word from memory into a vector register element. The effective address (EA) is calculated by adding the contents of general-purpose registers RA and RB, with the result ANDed with 0xFFFF_FFFF_FFFF_FFFC to ensure it is aligned to a 4-byte boundary. The byte at the calculated EA is placed into the specified position in VSR[VRT+32], depending on the endianness.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
EA ←EA & 0xFFFF_FFFF_FFFF_FFFC
eb ←EA.bit[60:63]
VSR[VRT+32] ←undefined
if Big-Endian byte ordering then
    VSR[VRT+32].byte[eb:eb+3] ←MEM(EA,4)
else
    VSR[VRT+32].byte[12-eb:15-eb] ←MEM(EA,4)

Programming Note

The lvewx instruction loads a word from memory into a vector register element. Ensure the effective address is aligned to a 4-byte boundary by ANDing with 0xFFFF_FFFF_FFFF_FFFC. This instruction requires the VEC bit in the MSR to be set; otherwise, it raises a Vector_Unavailable exception. Be aware of endianness when placing the byte into the vector register.

Example

lvewx v1, r4, r5

Encoding

Binary Layout
0
0
VRT
6
RA
11
RB
16
 
Format X-form
Opcode 0x7C00008E
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • VRT
    Target Vector Register
  • RA
    Source General Purpose Register
  • RB
    Source General Purpose Register