lvewx

Load Vector Element Word Indexed

lvewx VRT,RA,RB

Loads a word from memory into a vector register element.

Encoding

Binary Layout

0

0:5

VRT

6:10

RA

11:15

RB

16:31

 

Format X-form

Opcode 0x7C00008E

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register

Example

lvewx v1, r4, r5

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a word (32 bits) from memory at address RA+RB (aligned to 4-byte boundary) and stores it in a vector register element in VRT, with zero padding in remaining doublewords. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

Operation

EA ← (RA = 0 ? 0 : GPR(RA)) + GPR(RB)
word_index ← EA[30:31]
VRT ← (0x00000000000000000000000000000000 || [EA & ~0x3])
VRT[word_index] ← [EA & ~0x3]

Programming Note

The lvewx instruction loads a word from memory into a vector register element. Ensure the effective address is aligned to a 4-byte boundary by ANDing with 0xFFFF_FFFF_FFFF_FFFC. This instruction requires the VEC bit in the MSR to be set; otherwise, it raises a Vector_Unavailable exception. Be aware of endianness when placing the byte into the vector register.