vcfuged

Vector Centrifuge Doubleword

vcfuged vD, vA, vB

Separates bits of source into two groups based on mask (Power10).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1357

21:31

Format VX-form

Opcode 0x1000054D

Extension VMX (AltiVec)

Operands

vD
Target
vA
Source
vB
Mask
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Mask Vector Register

Example

vcfuged vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vcfuged, the bits of VSR[VRA+32] are rearranged based on the mask in VSR[VRB+32]. Bits corresponding to 1s in the mask are placed in the rightmost positions, and other bits are placed in the leftmost positions.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    ptr0 ←0
    ptr1 ←0
    do j = 0 to 63
        if VSR[VRB+32].dword[i].bit[j]=0b0 then do
            result.bit[ptr0] ←
               VSR[VRA+32].dword[i].bit[j]
            ptr0 ←ptr0 + 1
        end
        if VSR[VRB+32].dword[i].bit[63-j]=1 then do
            result.bit[63-ptr1] ←
               VSR[VRA+32].dword[i].bit[63-j]
            ptr1 ←ptr1 + 1
        end
    end
    VSR[VRT+32].dword[i] ←result
end

Programming Note

The vcfuged instruction rearranges bits in a vector register based on a mask from another vector register. Ensure the Vector Facility is enabled by checking and setting the MSR.VEC bit. The operation processes each doubleword independently, moving bits to the right or left based on the mask's 0s and 1s. Be cautious of alignment issues when accessing vector registers.