vexpanddm

Vector Expand Doubleword Mask

vexpanddm vD, vB

Expands bits from a GPR mask into a doubleword-element vector.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1794

21:31

Format VX-form

Opcode 0x10030642

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source

Example

vexpanddm vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Expands individual bits from a source vector register into doubleword-sized elements in the destination vector register, where each bit controls whether the corresponding doubleword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.

Operation

for i in 0 to 3 do
  if vB[i] = 1 then
    vD[i*64:(i+1)*64-1] ← 0xFFFFFFFFFFFFFFFF
  else
    vD[i*64:(i+1)*64-1] ← 0x0000000000000000
  end if
end for

Programming Note

This instruction is useful for creating masks where each doubleword element in the target vector register is either all ones or all zeros based on the least significant bit of the corresponding source vector element. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1; otherwise, a Vector Unavailable exception will be raised. The instruction operates on doubleword elements, so ensure proper alignment and indexing when using this instruction.