xsmuldp
VSX Scalar Multiply Double-Precision
Multiplies two double-precision floating-point numbers and places the result in a vector register.
Details
The xsmuldp instruction multiplies the contents of two double-precision floating-point numbers located in VSR registers and stores the result in another VSR register. The product is normalized and rounded to double-precision format using the rounding mode specified by FPSCR.RN.
Pseudocode Operation
if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_MULTIPLY(src1, src2)
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vximz_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FR ← inc_flag
FPSCR.FI ← xx_flag
else do
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0
end
FPSCR.FPRF ← fprf_CLASS_BFP64(result)
VSR[32×TX+T].dword[0] ← resultProgramming Note
Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.
Example
Encoding
Operands
-
XT
Target Vector-Specific Register -
XA
Source Vector-Specific Register -
XB
Source Vector-Specific Register