xsmuldp

VSX Scalar Multiply Double-Precision

xsmuldp XT,XA,XB

Multiplies two double-precision floating-point numbers and places the result in a vector register.

Encoding

Binary Layout

111100

000000

Format XX3-form

Opcode 0xF0000180

Extension VSX

Operands

XT
Target Vector-Specific Register
XA
Source Vector-Specific Register
XB
Source Vector-Specific Register

Example

xsmuldp vs1, vs2, vs3

Registers Altered

FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.FX, FPSCR.OX, FPSCR.UX, XX, VXSNAN, VXIMZ

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the scalar double-precision floating-point value in VSR[XA] by the scalar double-precision floating-point value in VSR[XB], storing the result in VSR[XT]. The operation follows IEEE 754 semantics; FPSCR is updated with exception flags and rounding control. This VSX instruction requires the VSX extension.

Operation

XT ← VSR[XA] × VSR[XB]
FPSCR ← updated with exception flags and rounding

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.