lvx

Load Vector Indexed

lvx vD, RA, RB

Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).

Details

The lvx instruction loads a quadword from the effective address (EA) calculated by adding the contents of registers RA and RB, and places it into VSR[VRT+32]. The EA is masked with 0xFFFF_FFFF_FFFF_FFF0 to ensure it is aligned on a 16-byte boundary.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
EA ←EA & 0xFFFF_FFFF_FFFF_FFF0
VSR[VRT+32] ←MEM(EA, 16)

Programming Note

The Load Vector Element instructions load the specified element into the same location in the target register as the location into which it would be loaded using the Load Vector instruction.

Example

lvx v1, r3, r4

Encoding

Binary Layout
31
0
VRT
6
RA
11
RB
16
103
21
/
31
 
Format X-form
Opcode 0x7C00000E
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target Vector Register
  • RA
    Base Register
  • RB
    Index Register
  • Vt
    Target Vector Register
  • Rb
    Base General Purpose Register
  • VRT
    Target Vector Register