lvx

Load Vector Indexed

lvx vD, RA, RB

Loads a 128-bit vector from memory into a Vector Register. Address must be 16-byte aligned (bits 60-63 of effective address are ignored).

Encoding

Binary Layout

0:5

VRT

6:10

11:15

16:20

103

21:30

Format X-form

Opcode 0x7C0000CE

Extension VMX (AltiVec)

Operands

vD
Target Vector Register
RA
Base Register
RB
Index Register
Vt
Target Vector Register
Rb
Base General Purpose Register
VRT
Target Vector Register

Example

lvx v1, r3, r4

// Load aligned vector.

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Load Vector Indexed loads a 128-bit vector from memory at the address computed from RA and RB, placing the result in VRT. The effective address must be 16-byte aligned; the low 4 bits of the computed address are ignored. This is a VMX/AltiVec instruction requiring the Vector facility to be enabled.

Operation

EA ← (RA + RB) & 0xFFF...FF0
VRT ← [EA]

Programming Note

The Load Vector Element instructions load the specified element into the same location in the target register as the location into which it would be loaded using the Load Vector instruction.

lvx