lxvd2x

Load VSX Vector Doubleword*2 Indexed

lxvd2x XT, RA, RB

Loads a 128-bit vector from memory into a VSX register. Does NOT require 16-byte alignment (unlike lvx).

Encoding

Binary Layout

0:5

6:10

11:15

16:20

844

21:30

Format XX1-form

Opcode 0x7C000698

Extension VSX

Operands

XT
Target VSR (0-63)
RA
Base Register
RB
Index Register

Example

lxvd2x 32, r3, r4

// Unaligned 128-bit load to vs32 (v0).

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of the byte in storage at address EA+8×i+7 are placed into byte element 7 of load_data. When Little-Endian byte ordering is employed, the contents of the doubleword in storage at address EA+8×i are placed into load_data in such an order that; the contents of the byte in storage at address EA+8×i are placed into byte element 7 of load_data, and so forth until the contents of the byte in storage at address EA+8×i+7 are placed into byte element 0 of load_data. For each integer value i from 0 to 1, do the following.

Operation

if MSR.VSX=0 then VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
for i from 0 to 1 do
    VSR[32×TX+T].dword[i] ←MEM(EA+8×i, 8)

Programming Note

lxvd2x, lxvw4x, lxvh8x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.