fcfidu

Floating Convert from Unsigned Integer Doubleword

fcfidu FRT, FRB

Converts 64-bit Unsigned Int to Double.

Encoding

Binary Layout

63

0:5

FRT

6:10

0

11:15

FRB

16:20

974

21:30

/

31

 

Format X-form

Opcode 0xFC00079C

Extension Floating-Point

Operands

• FRT
  Target
• FRB
  Source

Example

fcfidu f1, f3

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Floating Convert from Unsigned Integer Doubleword converts the unsigned 64-bit integer held in FRB to a double-precision floating-point value and places the result in FRT. The conversion uses the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, and FI flags.

Operation

FRT ← (double)(uint64_t)FRB
Update FPSCR[FPRF, FR, FI]

Programming Note

The fcfidu instruction converts a 64-bit unsigned integer to a double-precision floating-point value. Be cautious of NaN inputs, which will result in zero with VXCVI set. Ensure the source register contains valid data; otherwise, unexpected results may occur. This instruction operates at user privilege level.