fctiw.

Floating Convert with round Double-Precision To Signed Word format (Record)

fctiw. FRT,FRB

Converts a float to a 32-bit signed integer (using the current rounding mode) and stores it in the lower half of the FPR.

Encoding

Binary Layout

0:5

FRT

6:10

11:15

FRB

16:20

21:30

Format X-form

Opcode 0xFC00001C

Extension Floating-Point

Operands

FRT
Target FPR
FRB
Source FPR
RT
Target Floating Point Register
RA
Source Floating Point Register

Example

fctiw f1, f2

// Convert float f2 to int in f1.

Registers Altered

FPSCR, (FR, FI, FX, XX, VXSNAN, VXCVI), CR1, (if, Rc=1), CR0

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts the double-precision floating-point value in FRB to a signed word using the specified rounding mode. If the result is out of range, it saturates to the maximum or minimum signed integer value.

Operation

round_mode ← FPSCRRN
tgt_precision ← '32-bit signed integer'

sign ← (FRB)0
if (FRB)1:11 = 2047 and (FRB)12:63 = 0 then goto Infinity Operand
if (FRB)1:11 = 2047 and (FRB)12 = 0 then goto SNaN Operand
if (FRB)1:11 = 2047 and (FRB)12 = 1 then goto QNaN Operand
if (FRB)1:11 > 1086 then goto Large Operand

if (FRB)1:11 > 0 then exp ← (FRB)1:11 - 1023   /* exp - bias */
if (FRB)1:11 = 0 then exp ← -1022
if (FRB)1:11 > 0 then frac0:64 ← 0b01 || (FRB)12:63 || 110   /* normal */
if (FRB)1:11 = 0 then frac0:64 ← 0b00 || (FRB)12:63 || 110   /* denormal */

rbit || xbit ← 0b00
for i=1,63-exp    /* do the loop 0 times if exp = 63 */
    frac0:64 || rbit || xbit ← 0b0 || frac0:64 || (rbit | xbit)
end

FRT ← Round Integer(sign, frac0:64, gbit, rbit, xbit, round_mode)

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.