fcfids

Floating Convert with round Signed Doubleword to Single-Precision format

fcfids FRT,FRB

Converts a 64-bit signed fixed-point operand in register FRB to single-precision floating-point.

Encoding

Binary Layout

59

0:5

FRT

6:10

0

11:15

FRB

16:20

846

21:30

/

31

 

Format X-form

Opcode 0xEC00069C

Extension Floating-Point

Operands

• FRT
  Target
• FRB
  Source

Example

fcfids f1, f3

Registers Altered

FPSCR (FPRF, FR, FI, FX, XX), CR1 (if Rc=1)

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The 64-bit signed fixed-point operand in register FRB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to single-precision, using the rounding mode specified by RN, and placed into register FRT.

Operation

FRT ← ConvertToFloat(FRB, RN)
SetFlags(FPRF, FR, FI)

Programming Note

Converting a signed integer word to single-precision floating-point can be accomplished by loading the word from storage using Load Float Word Algebraic and then using fcfids.