dsubq

Decimal Subtract Quad-Precision

dsubq vD, vA, vB

Subtracts two 128-bit DFP numbers.

Encoding

Binary Layout

63

0:5

vD

6:10

vA

11:15

vB

16:20

514

21:30

/

31

 

Format X-form

Opcode 0xFC000404

Extension Decimal Floating-Point

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

dsubq vd, va, vb

Registers Altered

FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Subtracts the 128-bit Decimal Floating-Point value in vB from vA, storing the result in vD. The operation follows DFP semantics, respecting the current rounding mode in FPSCR and producing an exact result or DFP exception as appropriate. The FPSCR is updated with exception flags.

Operation

vD ← vA - vB (DFP arithmetic)
FPSCR ← updated with exception flags (XX, ZX, UX, OX, IE)

Programming Note

The dsubq instruction is used for precise decimal subtraction of quad-precision numbers. Ensure that the operands are correctly aligned and formatted to avoid precision loss. The result's rounding mode is controlled by the FPSCR register, so verify DRN settings before execution. This operation requires floating-point privilege level.