fcfidus.

Floating Convert with round Unsigned Doubleword to Single-Precision format

fcfidus. FRT,FRB

Converts an unsigned doubleword integer in a floating-point register to a single-precision floating-point number, rounding the result.

Encoding

Binary Layout

111011

0:5

FRT

6:10

//

11:15

FRB

16:20

11110

21:30

01110

31

 

Format X-form

Opcode 0xEC00079C

Extension Floating-Point

Operands

• FRT
  Target Floating Point Register
• FRB
  Source Floating Point Register

Example

fcfidus. f1, f3

Registers Altered

FPSCR, CR0

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts the contents of the source floating-point register (FRB) from an unsigned doubleword integer to a single-precision floating-point number and stores it in the target floating-point register (FRT).

Operation

FRT <- ConvertToSinglePrecision(FRB, unsigned)

Programming Note

Use fcfidus. when converting unsigned 64-bit integers to single-precision floats. Ensure the source register contains a valid unsigned integer; otherwise, the result is undefined. This instruction operates at user privilege level and does not raise exceptions for invalid input values.