fcfidus

Floating Convert from Unsigned Integer Doubleword Single

fcfidus FRT, FRB

Converts 64-bit Unsigned Int to Single.

Encoding

Binary Layout

59

0:5

FRT

6:10

0

11:15

FRB

16:20

974

21:30

/

31

 

Format X-form

Opcode 0xEC00079C

Extension Floating-Point

Operands

• FRT
  Target
• FRB
  Source

Example

fcfidus f1, f3

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Floating Convert from Unsigned Integer Doubleword Single converts the unsigned 64-bit integer held in FRB to a single-precision floating-point value and places the result in FRT. The conversion uses the current rounding mode in FPSCR. FPSCR is updated with FPRF, FR, and FI flags.

Operation

FRT ← (float)(uint64_t)FRB
Update FPSCR[FPRF, FR, FI]

Programming Note

The fcfidus instruction is used to convert a 64-bit unsigned integer from one register to a single-precision floating-point number in another register. Ensure the source register contains a valid unsigned integer and that the rounding mode specified by RN is appropriate for your application. This instruction alters several fields in the FPSCR, so be aware of potential flag changes that may affect subsequent operations.