fmadd.

Floating Multiply-Add (Record)

fmadd. FRT,FRA,FRC,FRB

Performs (A * C) + B with a single rounding step. (The classic FMA).

Encoding

Binary Layout

63

0:5

FRT

6:10

FRA

11:15

FRB

16:20

FRC

21:25

29

26:30

Rc

31

 

Format A-form

Opcode 0xFC00003A

Extension Floating-Point

Operands

• FRT
  Target FPR
• FRA
  Multiplier
• FRC
  Multiplicand
• FRB
  Addend

Example

fmadd f1, f2, f3, f4

// f1 = (f2 * f3) + f4

Registers Altered

FPSCR, CR1, CR0

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction multiplies the contents of register FRA by the contents of register FRC, then adds the result to the contents of register FRB. The final result is placed into register FRT.

Operation

FRT ←[(FRA)×(FRC)] + (FRB)
if 'fmadd.' then
    CR1 <- result class and sign

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.