fmul

Floating Multiply

fmul FRT,FRA,FRC
fmul. FRT,FRA,FRC

Multiplies the contents of two floating-point registers and places the result into another register.

Details

The floating-point operand in register FRA is multiplied by the floating-point operand in register FRC. The result is rounded to the target precision under control of RN and placed into register FRT.

Pseudocode Operation

if 'fmul' then
    FRT <- (FRA) * (FRC)
else if 'fmul.' then
    FRT <- (FRA) * (FRC)

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

fmul f1, f2, f3

Encoding

Binary Layout
63
0
FRT
6
FRA
11
00000
16
FRC
21
25
Rc
 
Format A-form
Opcode 0xFC000032
Extension Floating-Point
Registers Altered FPSCR, CR1, CR0

Operands

  • FRT
    Target FPR
  • FRA
    Source FPR A
  • FRC
    Source FPR C