dcbtst

Data Cache Block Touch for Store

dcbtst TH, RA, RB

Provides a hint that describes a block or data stream to which the program may perform a store access.

Encoding

Binary Layout

31

0:5

TH

6:10

RA

11:15

RB

16:20

246

21:30

/

31

 

Format X-form

Opcode 0x7C0001EC

Extension Base

Operands

• TH
  Hint
• RA
  Base
• RB
  Index

Example

dcbtst 0, r4, r5

Related

Across architectures

Cache Prefetch Hint : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Issues a cache hint indicating that a data block or stream will be accessed for storage (write). The instruction takes a hint field (TH) and an effective address (RA + RB) but does not load data into cache; it merely communicates intent to the cache hierarchy. No registers are modified and no condition codes are affected.

Operation

EA ← (RA) + (RB)
// Hint to cache management that block at EA will be stored to
// No actual load or register modification occurs

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
dcbtstds RA,RB,TH	dcbtst RA,RB,TH
dcbtstt RA,RB	dcbtst RA,RB,0b10000

Programming Note

See the Programming Notes at the beginning of this section.