xvi8ger4spp

VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturation Positive multiply, Positive accumulate

xvi8ger4spp AT,XA,XB

Performs a vector-scalar operation on 8-bit signed and unsigned integers with saturation.

Details

The xvi8ger4spp instruction performs a vector-scalar operation on 8-bit signed and unsigned integers with saturation. It multiplies corresponding elements of two vectors and accumulates the results into an accumulator, with saturation handling for overflow.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

if 'xvi8ger4spp' then do
   PMSK ←0b1111
   XMSK ←0b1111
   YMSK ←0b1111
end

do i = 0 to 3
   do j = 0 to 3
      if XMSK.bit[i] & YMSK.bit[j] then do
         prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[0]) *
                                       EXTZ(VSR[32×BX+B].word[j].byte[0])
         prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[1]) *
                                       EXTZ(VSR[32×BX+B].word[j].byte[1])
         prod2 ←(PMSK.bit[2]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[2]) *
                                       EXTZ(VSR[32×BX+B].word[j].byte[2])
         prod3 ←(PMSK.bit[3]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].byte[3]) *
                                       EXTZ(VSR[32×BX+B].word[j].byte[3])

         psum ←prod0 + prod1 + prod2 + prod3

         ACC[AT][i].word[j] ←si32_CLAMP( psum + EXTS(ACC[AT][i].word[j] )

         if sat_flag=1 then VSCR.SAT ←1
      end
      else
         ACC[AT][i][j] ←0x0000_0000
   end
end

Programming Note

This instruction is used for performing vector-scalar operations on 8-bit signed and unsigned integers, multiplying corresponding elements of two vectors and accumulating the results into an accumulator with saturation handling. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a 'VSX_Unavailable' exception. The operation involves multiple steps of multiplication and accumulation, which can be computationally intensive; consider optimizing vector sizes and operations for performance.

Example

xvi8ger4spp acc0, vs2, vs3

Encoding

Binary Layout
0
0
AT
6
XA
11
XB
16
16
21
21
26
29
29
30
30
31
31
 
Format XX3-form
Opcode 0xEC000318
Extension VSX
Registers Altered VSCR, ACC

Operands

  • AT
    Target Vector Register
  • XA
    Source Vector Register
  • XB
    Source Vector Register