xssubsp

VSX Scalar Subtract Single-Precision

xssubsp XT, XA, XB

Subtracts the contents of two single-precision floating-point values and places the result in a vector register.

Details

The instruction subtracts the double-precision floating-point value in doubleword element 0 of VSR[XB] from the double-precision floating-point value in doubleword element 0 of VSR[XA], negates the result, and adds it to src1. The result is normalized and rounded to single-precision using the rounding mode specified by RN.

Pseudocode Operation

if src1 is NaN or src2 is NaN then
    v <- Q(src1) if src1 is SNaN else Q(src2) if src2 is SNaN else dQNaN
else if src1 is +Infinity and src2 is +Infinity then
    v <- +Infinity
    vxisi_flag <- 1
else if src1 is -Infinity and src2 is -Infinity then
    v <- -Infinity
    vxisi_flag <- 1
else if src1 is NZF and src2 is NZF then
    v <- S(src1, src2)
else if src1 is Zero and src2 is Zero then
    v <- Rezd
else if src1 is +Zero and src2 is -Zero then
    v <- +Zero
else if src1 is -Zero and src2 is +Zero then
    v <- -Zero
else if src1 is NZF and src2 is Zero then
    v <- src1
else if src1 is Zero and src2 is NZF then
    v <- -src2
else if src1 is +Infinity and src2 is NZF then
    v <- +Infinity
    vxisi_flag <- 1
else if src1 is NZF and src2 is +Infinity then
    v <- -Infinity
    vxisi_flag <- 1
else if src1 is -Infinity and src2 is NZF then
    v <- -Infinity
    vxisi_flag <- 1
else if src1 is NZF and src2 is -Infinity then
    v <- +Infinity
    vxisi_flag <- 1
else if src1 is QNaN or src2 is QNaN then
    v <- src1 if src1 is QNaN else src2 if src2 is QNaN else dQNaN
else if src1 is SNaN or src2 is SNaN then
    v <- Q(src1) if src1 is SNaN else Q(src2) if src2 is SNaN else dQNaN
    vxsnan_flag <- 1

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xssubsp vs1, vs2, vs3

Encoding

Binary Layout

Format XX3-form

Opcode 0xF0000008

Extension VSX

Registers Altered FPSCR, VSR[XT]

Operands

XT
Target
XA
Src A
XB
Src B