macchw

Multiply Accumulate Cross Halfword

macchw RT, RA, RB

Multiply bottom half of RA by top half of RB, add to RT.

Encoding

Binary Layout

4

0:5

RT

6:10

RA

11:15

RB

16:20

172

21:30

0

31

 

Format XO-form

Opcode 0x10000158

Extension Embedded

Operands

• RT
  Acc/Dest
• RA
  Src A
• RB
  Src B

Example

macchw r3, r4, r5

Related

More in Embedded

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the low halfword (bits 48-63) of RA by the high halfword (bits 0-15) of RB and adds the signed 32-bit product to the low 32 bits of RT, placing the result back in the low 32 bits of RT. This is part of the embedded (e200/e500) category. The instruction does not affect condition registers or XER unless an extended variant is used.

Operation

prod ← EXTS(RA[48:63], 32) * EXTS(RB[0:15], 32); RT[32:63] ← RT[32:63] + prod[0:31]