mfocrf

Move From One Condition Register Field

mfocrf RT, FXM

Moves a single CR field to a GPR.

Encoding

Binary Layout

31

0:5

RT

6:10

FXM

11:18

19

19:30

/

31

 

Format XFX-form

Opcode 0x7C100026

Extension Base

Operands

• RT
  Target
• FXM
  Mask

Example

mfocrf r3, 0xFF

Registers Altered

CR

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Moves a single condition register field to a GPR, using FXM as a mask to select which CR field (CR0-CR7) is read. The FXM field must have only one bit set; the selected 4-bit CR field is placed in bits [0:3] of RT, with all other GPR bits zeroed.

Operation

// Move CR field selected by FXM to GPR bits [0:31]
RT ← 0
for i in 0 to 7:
  if FXM[i] = 1 then
    RT[i*4:(i+1)*4] ← CR[i*4:(i+1)*4]

Programming Note

The mfocrf instruction is used to extract a specific condition register field into a general-purpose register. Ensure that exactly one bit in the FXM field is set to avoid undefined behavior. This instruction operates at user privilege level and does not generate exceptions under normal conditions.