machhw

Multiply Accumulate High Halfword

machhw RT, RA, RB

Multiply top half of RA by top half of RB, add to RT.

Encoding

Binary Layout

4

0:5

RT

6:10

RA

11:15

RB

16:20

44

21:30

0

31

 

Format XO-form

Opcode 0x10000058

Extension Embedded

Operands

• RT
  Acc/Dest
• RA
  Src A
• RB
  Src B

Example

machhw r3, r4, r5

Related

More in Embedded

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies the high halfword (bits 0-15) of RA by the high halfword of RB as signed integers, then adds the 32-bit product to RT and stores the result in RT. This is part of the Embedded (SPE) category and does not affect any condition or status registers.

Operation

product ← EXTS(RA[0:15]) × EXTS(RB[0:15])
RT ← RT + product