mfspr
Move From Special Purpose Register
Moves the contents of a special purpose register into a general-purpose register.
Details
The mfspr instruction moves the contents of a special purpose register (SPR) specified by the SPR field into the target general-purpose register RT. If the SPR is 32 bits long, the low-order 32 bits of RT receive the contents of the SPR and the high-order 32 bits are set to zero.
Pseudocode Operation
switch(n)
case(800, 802): RT ← BESCR
case(801, 803): RT ← 320 || BESCRU
case(808, 809, 810, 811):
if length(SPR(n)) = 64 then
RT ← SPR(n)
else
RT ← 320 || SPR(n)
default:
if spr0=0:
if MSRPR=1: Hypervisor Emulation Assistance interrupt
else: no operation (i.e., the instruction is treated as a no-op) when LPCREVIRT=0 and Hypervisor Emulation Assistance interrupt when LPCREVIRT=1 for all other SPRs
else:
if spr0=1:
if MSRPR=1: Privileged Instruction type Program interrupt
else: no operation (i.e., the instruction is treated as a no-op) when LPCREVIRT=0 and Hypervisor Emulation Assistance interrupt when LPCREVIRT=1
Programming Note
The SPR field denotes a Special Purpose Register, encoded as shown in the table below. If the SPR field contains a value from 808 through 811, the instruction specifies a reserved SPR, and is treated as a no-op; see Section 1.3.3, “Reserved Fields, Reserved Values, and Reserved SPRs”. Otherwise, the contents of the designated Special Purpose Register are placed into register RT. For Special Purpose Registers that are 32 bits long, the low-order 32 bits of RT receive the contents of the Special Purpose Register and the high-order 32 bits of RT are set to zero.
Extended Mnemonics
| Extended Mnemonic | Equivalent Instruction |
|---|---|
| mfxer | |
| mflr | |
| mfctr |
Example
Encoding
Operands
-
RT
Target Register -
SPR
Special Purpose Register ID