vsum4shs

Vector Sum-across Partial (1/4) Signed Halfword Saturate

vsum4shs vD, vA, vB

Sums every 2 halfwords into a word.

Details

The vsum4shs instruction performs a vector sum across quarter signed halfword saturate operation. It adds the signed integer values in two halfword elements of each word from VSR[VRA+32] to the corresponding signed integer value in the same word of VSR[VRB+32]. If the intermediate result exceeds 2^31 - 1 or is less than -2^31, it saturates to these limits and sets the SAT flag. The low-order 32 bits of each result are placed into the corresponding word elements of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
   temp ←EXTS(VSR[VRB+32].word[i])
   do j = 0 to 1
      temp ←temp + EXTS(VSR[VRA+32].word[i].hword[j])
   end
   VSR[VRT+32].word[i] ←si32_CLAMP(temp)
   VSCR.SAT ←sat_flag
end

Programming Note

The vsum4shs instruction is commonly used for performing saturated addition of signed halfwords within vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious with saturation handling as it can affect the results if intermediate sums exceed 32-bit integer limits.

Example

vsum4shs vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1608
21
 
Format VA-form
Opcode 0x10000648
Extension VMX (AltiVec)
Registers Altered MSR, VSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Accumulator