vsum4shs

Vector Sum-across Partial (1/4) Signed Halfword Saturate

vsum4shs vD, vA, vB

Sums every 2 halfwords into a word.

Details

Sums pairs of signed halfword elements from vA and accumulates into words in vB (accumulator), storing saturated results in vD. The instruction processes 2 halfword pairs per word, setting the saturation bit (VSCR[SAT]) if any result overflows. This is a Classic VMX (AltiVec) instruction.

Pseudocode Operation

for i in 0 to 3 do
  sum ← vA[i*2] + vA[i*2+1] + vB[i]
  vD[i] ← SATURATE_SIGNED_WORD(sum)
  if overflow then VSCR[SAT] ← 1
endfor

Programming Note

The vsum4shs instruction is commonly used for performing saturated addition of signed halfwords within vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Be cautious with saturation handling as it can affect the results if intermediate sums exceed 32-bit integer limits.

Example

vsum4shs vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
1608
21
 
Format VA-form
Opcode 0x10000648
Extension VMX (AltiVec)
Registers Altered MSR, VSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Accumulator